Programming Methods for a Nonvolatile Memory Device Using a Y-Scan Operation During a Verify Read Operation

ABSTRACT

Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programming the data into the memory cells, performing a verify read operation to determine whether the data has been successfully programmed into the memory cells, and performing a Y-scan operation while performing the verify read operation to sequentially scan and output data read from bit lines coupled to the memory cells.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of Korean Patent Application No.10-2005-0052484, filed on Jun. 17, 2005, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to nonvolatile memory devices and, moreparticularly, to flash memory devices,

2. Description of the Related Art

Electrically erasable and programmable flash memory can preserve dataeven when electric power is not provided. In particular, because suchflash memory has a string structure in which a plurality of flash memorycells are connected in series, NAND-type flash memory may facilitateintegration and can be provided at low cost. For these reasons,NAND-type flash memory has been used as data memory in diverse portableproducts.

A flash electrically erasable programmable read-only memory (EEPROM)cell transistor may be programmed or erased using the Fowler-Nordheim(FN) tunneling mechanism. An operation of erasing the cell transistormay be performed by applying a ground voltage of 0 V to a control gateof the cell transistor and applying a voltage (e.g., 20 V) higher than apower supply voltage to a semiconductor substrate (or bulk). Accordingto such a bias condition, a strong electric field may be formed betweena floating gate and a bulk due to a great voltage differencetherebetween. As a result, electrons in the floating gate are dischargedto the bulk due to an FN tunneling effect. Here, the threshold voltageof the erased cell transistor may shift to a negative value, forexample, −3 V. This state is defined as data “1” and an EEPROM cell inthis state is referred to as an “ON-cell.”

An operation of programming the cell transistor is performed by applyinga voltage (e.g., 18 V) higher than the power supply voltage to thecontrol gate and applying the ground voltage to a drain and the bulk.Under such a bias condition, electrons are injected into the floatinggate of the cell transistor due to the FN tunneling effect. Here, thethreshold voltage of the programmed cell transistor may shift to apositive value, for example, +1 V. This state is defined as data “0” andan EEPROM cell in this state is referred to as an “OFF-cell.”

FIG. 1 is a block diagram of a conventional NAND-type flash memorydevice. Referring to FIG. 1, the NAND-type flash memory device includesa memory cell array 10, a row selection circuit (or a row decodercircuit) 12, a page buffer circuit (or a data sensing and latchingcircuit) 14, and a column decoder circuit 16.

The memory cell array 10 includes a plurality of memory blocks BLK0through BLKn (where “n” is a positive integer), each of which includes aplurality of strings. As illustrated in FIG. 1, each string includes astring selection transistor (SST) connected to a corresponding bit line,e.g., BL0, a ground selection transistor (GST) connected to a commonsource line (CSL), and memory cells MC15 through MC0 connected betweenthe SST and the GST. The SST, the memory cells MC15 through MC0, and theGST are respectively connected to a string selection line (SSL), wordlines WL15 through WL0, and a ground selection line (GSL). Blockselection transistors BS17 through BS0 respectively corresponding to thelines, i.e., the SSL, the word lines WL15 through WL0, and the GSL arecontrolled in common by a block selection signal BS.

The row selection circuit 12 selects one word line (or one page) amongthe word lines WL0 through WL15 through the block selection transistorsBS0 through BS17. The page buffer circuit 14 temporarily stores data tobe stored in memory cells of the selected page or senses data stored inthe memory cells of the selected page. The page buffer circuit 14comprises a plurality of page buffers (or data sensing and latch blocks)respectively corresponding to columns, i.e., bit lines related with theselected page. Data bits sensed from the memory cells of the selectedpage are output through the column decoder circuit 16 in predeterminedunits (for example, in byte units (×8)).

FIG. 2 illustrates part of a conventional column decoder circuit. Thecolumn decoder circuit illustrated in FIG. 2 corresponds to a singledata line. The same circuit structure as that illustrated in FIG. 2 maybe provided to correspond to each of other data lines. In FIG. 2, areference character “ND_LAT” denotes a latch node of the page buffercircuit 14 shown in FIG. 1. First selection signals YA0 through YA15 aresequentially activated, and simultaneously, second selection signals YB0through YB15 are sequentially activated. For example, while each of thesecond selection signals YB0 through YB15 is activated, the firstselection signals YA0 through YA15 are sequentially activated. As can beseen from such a structure and control method, for example, a singledata bit DL0 is selected from among 256 latched data bits ND_LAT0through ND_LAT254.

A page size may increase to meet users' demands for increase in datainput/output speed. However, when the page size increases, the followingproblems may occur: As is known, a program/erase operation includes averify operation for determining whether a memory cell is normallyprogrammed or erased. During the verify operation, the memory cells,i.e., bit lines of the selected page are sequentially scanned. This scanoperation is referred to as “verification scan,”“column scan,” or“Y-scan”.

The erase operation generally takes a relatively long time (e.g., 2 ms).Accordingly, the erase operation is not usually restricted by time takenfor the Y-scan (hereinafter, referred to as “Y-scan time”). However,because the page program operation generally takes a relatively shorttime (e,g., 240 μs or less), the Y-scan time may not be ignored in thepage program operation. Moreover, because a page program includes analgorithm for preventing a memory cell from being excessivelyprogrammed, the Y-scan time is not ignorable.

FIG. 3 illustrates conventional programming operations. In stage 301, ahost sends data to a static random access memory (SRAM) to perform aprogram operation. When a command indicating sequential data input isapplied to a flash memory having an array of memory cells to beprogrammed, the SRAM transmits the data to a page buffer of the flashmemory and address data and sequential data are sequentially input to anaddress buffer circuit ad a page buffer circuit of a memory device instage 302. Thereafter, when a command indicating start of a programmingprocess is applied to the memory device, a high-voltage generationcircuit operates to generate high voltage to be applied to a gate instage 303. As described above, bit lines are set to a power supplyvoltage (or a program-inhibit voltage) or a ground voltage (or a programvoltage) according to data loaded into the page buffer circuit in stage304, which is referred to as a bit line setup operation. After the bitlines are set to the power supply voltage or the ground voltage, thehigh voltage generated by the high-voltage generation circuit is appliedto a selected word line and the program operation is executed in stage305. After a predetermined period of time under the above-described biascondition, a verify operation for reading data from selected celltransistors is performed. The verify operation includes program recovery(stage 306), verify read (stage 307), and Y-scan (stage 308). Theprogram recovery is a process of converting a voltage of a bit line intoa predetermined value for data read and includes discharging andprecharging the bit line. The verify read is a process of reading andlatching data of the bit line and may include development for readingthe data of the bit line, bit line sensing, data latching, and bit linerecovery. The Y-scan is a process of sequentially scanning andoutputting data read from memory cells, i.e., bit lines of a selectedpage.

When at least one cell transistor among the selected cell transistors isnot programmed sufficiently, the above-described programming process(including the bit line setup, the program execution, and the verifyread) is repeated according to a predetermined program loop in stages309 and 310. Here, a high voltage used in a subsequent program loop,e.g., a second program loop is set to be higher (for example, 0.4 Vhigher) than that used in a current program loop, e.g., a first programloop.

In the conventional programming operations, the Y-scan is executed afterthe verify read is completed. In this case, as described above, becausethe program operation is performed in a relatively short time, theY-scan time is not ignorable. Moreover, because the verify read isrepeated when the programming process is repeated, the Y-scan time maynot be ignored.

SUMMARY

Some embodiments of the present invention may provide programmingoperations for reducing a program time for a nonvolatile memory device.A nonvolatile semiconductor memory device may be programmed by receivingdata to be programmed into memory cells from a host, programming thedata into the memory cells, performing a verify read operation todetermine whether the data has been successfully programmed into thememory cells, and performing a Y-scan operation while performing theverify read operation to sequentially scan and output data read from bitlines coupled to the memory cells.

In other embodiments, the programming method is terminated if it isdetermined that the data has been successfully programmed into thememory cells. Programming the data is repeated if it is determined thatthe data has not been successfully programmed into the memory cells.

In still other embodiments, repeating programming comprises repeatingprogramming the data according to a predetermined loop until it isdetermined that the data has been successfully programmed into thememory cells.

In still other embodiments, repeating programming comprises repeatingprogramming the data using a voltage higher than a voltage used inprevious programming.

In still other embodiments, performing the verify read operationcomprises performing a bit line recovery operation in which the bitlines coupled to the memory cells are discharged to a ground voltagelevel. The Y-scan operation and the bit line recovery operation areperformed simultaneously.

In still other embodiments, performing the bit line recovery operationcomprises isolating each bit line from a data latch unit configured tolatch data read from the respective bit line so that a voltage level ofthe respective bit line does not influence the read data.

In still other embodiments, programming the data comprises generating ahigh voltage to be applied to a gate of each of the memory cells,setting each of the bit lines to one of a power supply voltage and aground voltage according to data loaded into a page buffer circuit, andapplying the high voltage to a selected word line coupled to the memorycells.

In still other embodiments, performing the verify read operationcomprises discharging each of the bit lines connected to respective onesof the memory cells to a ground voltage level, precharging each of thebit lines to a precharge voltage level, blocking a power supply voltageprovided to each of the bit lines so that current in each of the bitlines flows or does not flow according to an ON or OFF state ofrespective ones of the memory cells and a voltage level of each of thebit lines changes, sensing the voltage level of each of the bit lines,latching data sensed from each of the bit lines, and performing a bitline recovery operation by discharging each of the bit lines to theground voltage level. The Y-scan operation and the bit line recoveryoperation are performed simultaneously.

In still other embodiments, performing the bit line recovery operationcomprises isolating each bit line from a data latch unit configured tolatch data read from the respective bit line so that a voltage level ofthe respective bit line does not influence the read data.

In still other embodiments, the nonvolatile semiconductor memory deviceis a NAND-type flash memory device.

In further embodiments, programmed memory cells are read and adetermination is made whether programming has been successfullyperformed in a nonvolatile semiconductor memory device by blocking apower supply voltage provided to bit lines coupled to the memory cellsso that a voltage level of each of the bit lines changes according to anON or OFF state of respective ones of the memory cells, sensing andlatching data on each of the bit lines, performing a bit line recoveryoperation by discharging each of the bit lines to a ground voltagelevel, and performing a Y-scan operation to sequentially scan and outputdata read from the bit lines. The Y-scan operation and the bit linerecovery operation are performed simultaneously.

In still further embodiments, before blocking the power supply voltagethe following are performed: discharging each of the bit lines to theground voltage level and precharging each of the bit lines to apredetermined precharge voltage.

In still further embodiments, sensing and latching data on each of thebit lines comprises storing the data in a plurality of page buffers.

In still further embodiments, the following operations are performed:determining whether data output from each of the bit lines is a firstlogic value, determining that the programming has been normallyperformed when data output from all of the page buffers are the firstlogic value, and determining that the programming has not beensuccessfully performed when data output from at least one page bufferincludes a second logic value.

In still further embodiments of the present invention, performing thebit line recovery operation comprises isolating each bit line from adata latch unit configured to latch data read from the respective bitline so that a voltage level of the respective bit line does notinfluence the read data.

In still further embodiments of the present invention, the nonvolatilesemiconductor memory device is a NAND-type flash memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features of the present invention will be more readily understoodfrom the following detailed description of exemplary embodiments thereofwhen read in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a conventional NAND-type flash memorydevice;

FIG. 2 is a schematic that illustrates a part of a conventional columndecoder circuit;

FIG. 3 is a diagram that illustrates conventional programmingoperations;

FIG. 4 is a circuit diagram that illustrates a flash memory deviceincluding a page buffer, according to some embodiments of the presentinvention;

FIG. 5 is a flowchart that illustrates a verify read operation accordingto some embodiments of the present invention; and

FIG. 6 is a diagram that illustrates programming operations according tosome embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that there is no intent to limit theinvention to the particular forms disclosed, but on the contrary, theinvention is to cover all modifications, equivalents, and alternativesfalling within the spirit and scope of the invention as defined by theclaims. Like reference numbers signify like elements throughout thedescription of the figures.

As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless expressly stated otherwise. Itwill be further understood that the terms “includes,” “comprises,”“including,” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof. It will be understood thatwhen an element is referred to as being “connected” or “coupled” toanother element, it can be directly connected or coupled to the otherelement or intervening elements may be present. Furthermore, “connected”or “coupled” as used herein may include wirelessly connected or coupled.As used herein, the term “and/or” includes any and all combinations ofone or more of the associated listed items.

It will be understood that although the terms first and second are usedherein to describe various components, circuits, regions, layers and/orsections, these components, circuits, regions, layers and/or sectionsshould not be limited by these terms. These terms are only used todistinguish one component, circuit, region, layer or section fromanother component, circuit, region, layer or section. Thus, a firstcomponent, circuit, region, layer or section discussed below could betermed a second component, circuit, region, layer or section, andsimilarly, a second component, circuit, region, layer or section may betermed a first component, circuit, region, layer or section withoutdeparting from the teachings of the present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

The present invention is described herein with reference to flowchartand/or block diagram illustrations of memory devices and methods ofprogramming the same in accordance with exemplary embodiments of theinvention. These flowchart and/or block diagrams further illustrateexemplary operations for programming memory devices, in accordance withsome embodiments of the present invention. It should be noted that thefunction(s) noted in the blocks may occur out of the order noted in thefigures. For example, two blocks shown in succession may, in fact, beexecuted substantially concurrently or the blocks may sometimes beexecuted in the reverse order, depending on the functionality involved.

FIG. 4 is a circuit diagram of a NAND-type flash memory device includinga page buffer, according to some embodiments of the present invention.The NAND-type flash memory device includes a memory cell array 10, a rowdecoder 20, and a page buffer circuit 40.

The memory cell array 10 includes a plurality of strings 12 e and 12 oextending in a column direction. Each of the strings 12 e and 12 oincludes a string selection transistor (SST) having a gate connected toa string selection line (SSL) and a ground selection transistor (GST)having a gate connected to a ground selection line (GSL). Memory cellsMC0 through MC15 are connected in series between the SST and the GST. Acontrol gate of each of the memory cells MC0 through MC15 is connectedto a word line WLj. A drain of the SST is connected to a correspondingbit line BLe or BLo. A source of the GST is connected to a common sourceline (CSL).

FIG. 4 illustrates a part of the page buffer circuit 40 corresponding totwo bit lines BLe and BLo. The structure illustrated in FIG. 4 isprovided for the other bit line pairs. A single page buffer correspondsto two adjacent strings 12 e and 12 o included in the memory cell array10.

In the page buffer circuit 40 illustrated in FIG. 4, first and secondnodes N1 and N2 are respectively connected to the bit lines BLe and BLo.An NMOS transistor M1 is connected between the first node N1 and aground voltage and has a gate that receives a signal VBLe. An NMOStransistor M2 is connected between the second node N2 and the groundvoltage and has a gate that receives a signal VBLo. The NMOS transistorsM1 and M2 respectively adjust the voltage levels of the bit lines BLeand BLo, which are inverted when activated and reduce the likelihoodthat the page buffer circuit 40 may be influenced by high voltage whenthe high voltage is applied to the bit lines BLe and BLo.

An NMOS transistor M3 is connected between the first node N1 and a thirdnode N3. A signal BLSHFe is applied to a gate of the NMOS transistor M3.An NMOS transistor M4 is connected between the second node N2 and thethird node N3. A signal BLSHFo is applied to a gate of the NMOStransistor M4. A PMOS transistor M5 is connected between a power supplyvoltage and the third node N3. A signal PLOAD is applied to a gate ofthe PMOS transistor M5. An NMOS transistor M6 is connected between thethird node N3 and a fourth node N4. A signal BLSLT is applied to a gateof the NMOS transistor M6. Two inverters are connected between thefourth node N4 and a fifth node N5 and form a latch. An NMOS transistorM7 is connected between the fifth node N5 and a sixth node N6 and has agate connected to the third node N3. An NMOS transistor M8 is connectedbetween the sixth node N6 and the ground voltage. A signal LCH isapplied to a gate of the NMOS transistor M8. An NMOS transistor M9 isconnected between the fourth node N4 and the ground voltage. A signalPBRST is applied to a gate of the NMOS transistor M9. NMOS transistorsM10 and M11 are connected in series between the fourth node N4 and aseventh node N7. A signal YA and a signal YB are respectively applied togates of the NMOS transistors M10 and M11. The seventh node N7 isconnected to an output line DOUT.

FIG. 5 is a flowchart of a verify read operation 500 according to someembodiments of the present invention. The verify read operation 500 is aprocess of sensing data in a programmed memory cell and verifyingwhether the memory cell has been programmed correctly. When it isverified that at least one of the selected cell transistors is notsufficiently programmed, a programming process is repeated according toa predetermined program loop.

After a programming process is completed, a verify read starts inresponse to a command indicating the start of the verify read operation(S501). Bit lines are discharged (S502) and precharged (S503).Development is performed on the bit lines so that voltage levels differon the bit lines according to the states of memory cells (S504). Data onthe bit lines are sensed (S505) and the sensed data is latched (S506).While bit lines having different voltage levels are being recoveredaccording to the data (S507), the data read from the bit lines aresequentially scanned and output using a Y-scan (S508). The output datais verified to determine whether the programming process has beensuccessfully performed (S509).

In other words, in a verify read process, according to some embodimentsof the present invention, bit line recovery and Y-scan aresimultaneously performed. in contrast with a conventional verify readprocess in which the Y-scan is performed after the bit line recovery,i.e., the verify read, the additional time dedicated for the Y-scan canbe eliminated according to some embodiments of the present invention.Accordingly, when the programming process and the verify read processare performed many times, program time can be reduced.

Hereinafter, a verify read process, according to some embodiments of thepresent invention, will be described in detail with reference to FIGS. 4and 5. When the voltage level of the CSL increases to about 0.7 V due tocurrent flowing through many unprogrammed cells and a threshold voltage(Vth) of an insufficiently programmed memory cell is 0.3 V, a readvoltage (VREAD) is applied to the SSL and the GSL, 0.8 V is applied to aselected word line, and 4.5 V is applied to unselected word lines.

The signals BLSHFe and VBLe transition to the level of the power supplyvoltage (VDD) and the voltage level of the bit line BLe transitions tothe level of the ground voltage (VSS) (S502). As a result, the bit lineBLe is discharged. The signals VBLe and BLSLT transition from VDD toVSS, the signal VBLo remains at the VDD level, and the signal BLSHFetransitions from VDD to 1.5 V and then to 1.1 V lower than VDD (S503).In addition, the signal PLOAD is driven to a low level to precharge theselected bit line BLe. Then, VDD is applied to the bit line BLe via thePMOS transistor M5 and the bit line BLe is set to a precharge voltage.

The signals PLOAD, BLSHFe, and VBLe transition to the VSS level (S504).If a selected memory cell is an ON-cell, current in the bit line BLeflows out to the CSL. As a result, the voltage level of the bit line BLedrops. However, if the selected memory cell is an OFF-cell, the currentin the bit line BLe does not flow and the bit line BLe remains at thelevel of the precharge voltage.

At block S505, the signal PLOAD transitions to the VDD level, the signalBLSHFe transitions to a sensing voltage level, and the signal VBLeremains at the VSS level. Then, the voltage level of the bit line BLe istransmitted to the third node N3 via the transistor M3.

At block S506, the signals PLOAD, BLSHFe, and VBLe remain at the VDDlevel, the sensing voltage level, and the VSS level, respectively, andthe signal LCH transitions to the VDD level. Then, the voltage level ofthe third node N3 is latched, thereby determining the data. For example,when the read memory cell has been programmed normally, the memory cellbecomes the OFF-cell and the bit line BLe remains at the prechargevoltage level (S504). Accordingly, at block S506, the transistors M7 andM8 are turned on and the fourth node N4 is at a logic “1.” When the readmemory cell has not been programmed normally, the memory cell becomesthe ON-cell and the bit line BLe has a low voltage level (S504).Accordingly, at block S506, the transistor M7 is turned off and thefourth node N4 remains at a reset state, i.e., a logic “0.”

At block S507, the signals BLSHFe and VBLe transition to the VDD leveland, thus, the bit line BLe recovers to the VSS level. Here, the voltagelevel of the recovered bit line BLe does not influence the fourth nodeN4, and, therefore, the bit line recovery (S507) and the Y-scan (S508)can be performed simultaneously.

At block S508, the column selection signals YA and YB transition to theVDD level and, thus, data of the fourth node N4 is transmitted to theoutput line DOUT. In other words, bit line data are sequentially outputaccording to column selection signals. At block S509, it is determinedthat the output data is at the logic “1”. If data output from all pagebuffers are at logic “1,”then the programming process ends; but, ifotherwise, the programming process is repeated.

FIG. 6 illustrates programming operations according to some embodimentsof the present invention. The programming operations illustrated in FIG.6 are analogous to the conventional programming operations illustratedin FIG. 3, with the exception that Y-scan (stage 608) is performed whilethe verify read operation (stage 607) is being performed. In moredetail, the Y-scan starts at the beginning of bit line recovery duringthe verify read.

As described above, in a programming operation according to someembodiments of the present invention, a Y-scan is performed in parallelduring a verify read operation, and, therefore, the total program timecan be reduced by the duration of the Y-scan had it been performed inserial order with other programming operations. In particular, when aprogramming operation is repeated, Y-scan time is saved at eachrepetition, and, therefore, total program time may be greatly reduced.

In concluding the detailed description, it should be noted that manyvariations and modifications can be made to the preferred embodimentswithout substantially departing from the principles of the presentinvention. All such variations and modifications are intended to beincluded herein within the scope of the present invention, as set forthin the following claims.

1. A method of programming a nonvolatile semiconductor memory device,comprising: receiving data to be programmed into memory cells;programming the data into the memory cells; performing a verify readoperation to determine whether the data has been successfully programmedinto the memory cells; and performing a Y-scan operation whileperforming the verify read operation to sequentially scan and outputdata read from bit lines coupled to the memory cells.
 2. The method ofclaim 1, further comprising terminating the programming method if it isdetermined that the data has been successfully programmed into thememory cells; and repeating programming the data if it is determinedthat the data has not been successfully programmed into the memorycells.
 3. The programming method of claim 2, wherein repeatingprogramming comprises repeating programming the data according to apredetermined loop until it is determined that the data has beensuccessfully programmed into the memory cells.
 4. The programming methodof claim 3, wherein repeating programming comprises repeatingprogramming the data using a voltage higher than a voltage used inprevious programming.
 5. The programming method of claim 1, whereinperforming the verify read operation comprises: performing a bit linerecovery operation in which the bit lines coupled to the memory cellsare discharged to a ground voltage level; and wherein the Y-scanoperation and the bit line recovery operation are performedsimultaneously.
 6. The programming method of claim 5, wherein performingthe bit line recovery operation comprises: isolating each bit line froma data latch unit configured to latch data read from the respective bitline so that a voltage level of the respective bit line does notinfluence the read data.
 7. The programming method of claim 1, whereinprogramming the data comprises: generating a high voltage to be appliedto a gate of each of the memory cells; setting each of the bit lines toone of a power supply voltage and a ground voltage according to dataloaded into a page buffer circuit; and applying the high voltage to aselected word line coupled to the memory cells.
 8. The programmingmethod of claim 1, wherein performing the verify read operationcomprises: discharging each of the bit lines connected to respectiveones of the memory cells to a ground voltage level; precharging each ofthe bit lines to a precharge voltage level; blocking a power supplyvoltage provided to each of the bit lines so that current in each of thebit lines flows or does not flow according to an ON or OFF state ofrespective ones of the memory cells and a voltage level of each of thebit lines changes; sensing the voltage level of each of the bit lines;latching data sensed from each of the bit lines; and performing a bitline recovery operation by discharging each of the bit lines to theground voltage level; wherein the Y-scan operation and the bit linerecovery operation are performed simultaneously.
 9. The programmingmethod of claim 8, wherein performing the bit line recovery operationcomprises: isolating each bit line from a data latch unit configured tolatch data read from the respective bit line so that a voltage level ofthe respective bit line does not influence the read data.
 10. Theprogramming method of claim 1, wherein the nonvolatile semiconductormemory device is a NAND-type flash memory device.
 11. A method ofreading programmed memory cells and determining whether programming hasbeen successfully performed in a nonvolatile semiconductor memorydevice, comprising: blocking a power supply voltage provided to bitlines coupled to the memory cells so that a voltage level of each of thebit lines changes according to an ON or OFF state of respective ones ofthe memory cells; sensing and latching data on each of the bit lines;performing a bit line recovery operation by discharging each of the bitlines to a ground voltage level; and performing a Y-scan operation tosequentially scan and output data read from the bit lines; wherein theY-scan operation and the bit line recovery operation are performedsimultaneously.
 12. The method of claim 11, further comprising, beforeblocking the power supply voltage: discharging each of the bit lines tothe ground voltage level; and precharging each of the bit lines to apredetermined precharge voltage.
 13. The method of claim 11, whereinsensing and latching data on each of the bit lines comprises: storingthe data in a plurality of page buffers; and wherein the method furthercomprises: determining whether data output from each of the bit lines isa first logic value; determining that the programming has been normallyperformed when data output from all of the page buffers are the firstlogic value; and determining that the programming has not beensuccessfully performed when data output from at least one page bufferincludes a second logic value.
 14. The method of claim 11, whereinperforming the bit line recovery operation comprises: isolating each bitline from a data latch unit configured to latch data read from therespective bit line so that a voltage level of the respective bit linedoes not influence the read data.
 15. The method of claim 11, whereinthe nonvolatile semiconductor memory devices is a NAND-type flash memorydecive.